Semiconductor chip with seal ring and sacrificial corner pattern

ABSTRACT

A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No. 12/410,170, filed on Mar. 24, 2009, the contents of which is incorporated herein by reference. U.S. application Ser. No. 12/410,170 is a Continuation of U.S. application Ser. No. 11/220,603, filed on Sep. 8, 2005, now U.S. Pat. No. 7,605,448, and claims the benefit of priority of Japanese Application No. 2004-264014, filed on Sep. 10, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device that includes a low dielectric constant film.

2. Description of the Background Art

With progresses in the miniaturization of semiconductor devices, the parasitic capacitance of copper wires has become approximately the same as the input/output capacitance of transistors, preventing increase in the speed of the device operation. Therefore, ways to introduce an insulating film, of which the relative dielectric constant is lower than that of a conventional silicon oxide (SiO₂, specific dielectric constant k˜4), have been actively sought. When relative dielectric constant k becomes small, however, the physical strength of an insulating film becomes inferior. In particular, when relative dielectric constant k becomes smaller than 3.5, sufficient physical strength cannot be maintained, leading to a problem. In the following, a film of which relative dielectric constant k is smaller than 3.5 is referred to as “low dielectric constant film,” in the present invention.

During heat cycle testing, after semiconductor devices have been packaged, temperature is changed, for example, from −65° C. to 150° C., and therefore, low dielectric constant films receive stress from resin portions, and as a result, in some cases, the low dielectric constant films peel. The lower the physical strength of a low dielectric constant film, the more significant peeling becomes. In addition, as for the location of peeling, it is particularly significant in the vicinity of chip corners, where stress concentrates.

In general, when moisture enters into the inside of a chip of a semiconductor device, the operation properties of the device deteriorate, and for this reason, a pattern that is referred to as a seal ring (also referred to as “guard ring”) is formed, in order to prevent entering of moisture from sides on the outer periphery of the chip. The seal ring is arranged in closed loop form in a plan view, where metal portions, such as contacts and wires that are used within the chip, are aligned in the upward and downward direction, and these layers are connected to each other through a structure in trench form that is also made of metal, so that a metal wall is formed. In a plan view, the seal ring becomes rectangular, with an outer periphery that is constantly spaced from the outer periphery of the chip.

When a low dielectric constant film is destroyed due to stress that is received from resin, as described above, cracking eventually progresses and reaches the seal ring. When cracking reaches the seal ring, the seal ring is easily destroyed. Once the seal ring is destroyed, moisture enters into the inside of the chip, causing a failure in the operation of the device. Furthermore, in extreme cases, cracking may progress as much as 500 μm and, in some cases, directly cut wires inside the chip.

In order to prevent destruction of the seal ring by cracking, several technologies have been proposed. U.S. Pat. No. 6,365,958, for example, discloses an arrangement of a member having a structure where a number of layers of lattice wires are arranged so as to overlap in the upward and downward direction, and lattice wires which are on top of one another are connected by means of vias that are made of metal outside of the seal ring as a sacrifice pattern for stopping the progress of cracking. U.S. Pat. No. 5,572,067 discloses an arrangement of a sacrifice corner structure where a lower layer wire that is parallel to the direction toward the center from the corner of the chip and an upper layer wire that is oriented perpendicular to this cross each other and are connected to each other by means of a via in a chip corner portion. U.S. Patent Publication No. 2004/0002198 discloses the placement of dummy metal patterns where a non-quadrilateral seal ring is used and placed in a corner portion of the chip, where a lower layer wire and an upper layer wire are connected in lattice form on both sides of the seal ring.

Japanese Patent Laying-Open No. 2004-172169 discloses a reinforcing pattern where a lower layer wire and an upper layer wire are connected through a via and an arrangement of a reinforcing pattern in wall form made of copper in the vicinity of a chip corner.

Even in the case where a structure that becomes a sacrifice pattern is arranged in the vicinity of a chip corner in accordance with a proposed technology, such as those that have been as described above, destruction of the seal ring by cracking cannot be sufficiently prevented. In addition, when the sacrifice pattern is made too great, a problem arises where the area on which circuits or the like are arranged becomes too small.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor device which can prevent destruction of a seal ring by cracking more efficiently and without fail.

In order to achieve the aforementioned object, a semiconductor device according to the present invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, and which includes a seal ring protrusion provided with one or more seal rings that is a moisture blocking wall in closed loop form in a plan view, and in which at least one of the seal rings is in inward protruding form in the vicinity of a chip corner.

The above described and other objects, characteristics, aspects and advantages of this invention will be clarified in the following detailed description of this invention, and are best understood in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a portion of a semiconductor device and illustrating the state of progress of cracking that has been found by the inventors;

FIG. 2 is a plan view showing a portion of a semiconductor device and illustrating the state of progress of cracking that has been found by the inventors;

FIG. 3 is a first view illustrating the properties of a crack that has been found by the inventors;

FIG. 4 is a second view illustrating the properties of a crack that has been found by the inventors;

FIG. 5 is a plan view showing a portion of a semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a cross-sectional view showing a portion of a semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a cross-sectional view showing a portion of a semiconductor device in another example according to the first embodiment of the invention;

FIG. 8 is a cross-sectional view showing a portion of a semiconductor device in still another example according to the first embodiment of the invention;

FIG. 9 is a plan view showing a portion of a semiconductor device according to the second embodiment of the present invention;

FIG. 10 is a plan view showing a portion of a semiconductor device according to the third embodiment of the present invention;

FIG. 11 is a plan view showing a portion of a semiconductor device according to the fourth embodiment of the present invention;

FIG. 12 is a plan view showing a portion of a semiconductor device according to the fifth embodiment of the present invention; and

FIG. 13 is a plan view showing a portion of a semiconductor device according to the sixth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First, prior to making the present invention, the inventors examined in detail how cracking occurs. An actual state where cracking has occurred that was found as a result is described with reference to FIGS. 1 and 2. FIG. 1 shows a cross-sectional view in the vicinity of a chip corner of a semiconductor device. A silicon oxide film 101, a silicon carbo-nitride film 102, a silicon oxide film 103, a silicon carbo-nitride film 104 a, a low dielectric constant film 105 a, a silicon carbo-nitride film 104 b, a low dielectric constant film 105 b, a silicon carbo-nitride film 104 c, a low dielectric constant film 105 c, a silicon carbo-nitride film 104 d, a silicon oxide film 106, a silicon carbo-nitride film 104 e, a silicon oxide film 107 a, a silicon oxide film 107 b and a silicon nitride film 108 are layered in this order on the upper side of a semiconductor device substrate 100. A contact 110 is arranged so as to penetrate through silicon oxide film 101. A copper wire 111 is arranged on the upper side of silicon oxide film 101. An interlayer connection portion 112 is provided so as to penetrate through low dielectric constant film 105 a and be connected to copper wire 111 from the top. A copper wire 113 is arranged so as to be buried in low dielectric constant film 105 a on the upper side of interlayer connection portion 112. Furthermore, the same structure is repeated in the upward direction, so that an interlayer connection portion 114, a copper wire 115, an interlayer connection portion 116 and a copper wire 117 are sequentially arranged. An interlayer connection portion 118 is arranged so as to penetrate through silicon oxide film 106 and be connected to copper wire 117 from the top. A copper wire 119 is arranged so as to be buried in the silicon oxide film on the upper side of interlayer connection portion 118. An interlayer connection portion 120 is arranged so as to penetrate through silicon oxide film 107 a and be connected to copper wire 119 from the top. An aluminum wire 121 is arranged on the upper side of interlayer connection portion 120. Aluminum wire 121 is arranged so as to be placed on the upper side of silicon oxide film 107 a, and is covered with silicon oxide film 107 b. A silicon nitride film peeling preventing trench 122 is provided by digging out a portion of silicon oxide film 107 b and silicon nitride film 108 in the vicinity of the end of the chip. The contact, copper wires, interlayer connection portions and aluminum wire from contact 110 to aluminum wire 121 are in wall form, and form a seal ring 123 for preventing moisture from entering.

During heat cycle testing, a shear force is applied in the direction of arrow 2 due to contraction of the resin (not shown) that covers the upper side. Low dielectric constant films have low physical strength, and therefore, a crack 1 occurs, originating from a chip corner. The inventors have examined cracking in low dielectric constant films in detail, and as a result, have found the following.

Firstly, the inventors have found that cracks, such as crack 1, easily occur, particularly in interfaces on the lower side of low dielectric constant films. Furthermore, the inventors ascertained that the probability of cracks such as crack 1 occurring in the low dielectric constant film that is the lowest from among a number of low dielectric constant films is the highest.

Secondly, the actual state of a crack while progressing is clarified in a plan view. FIG. 2 shows a plan view of this semiconductor device. Though conventionally, it has been believed that the ends of cracks originating from chip corners 4 progress in the direction of arrows 20 in a straight line 22 which forms an angle of 45° relative to two sides that form a chip corner 4, the inventors have found that the ends of cracks are not in a simple straight line, but actually progress in such a manner that they spread from a bent line 24 a to a bent line 24 b in the direction of arrows 21.

Thirdly, it has also been found that cracks occur in the interface on the lower side of low dielectric constant film 105 a, as shown in FIG. 3, and progress along this interface without changing course, and in addition, avoid copper wire 111 so as to pass over copper wire 111 and further progress along low dielectric constant film 105 b when they encounter copper wire 111 which completely blocks low dielectric constant film 105 a after progressing some distance, as shown in FIG. 4.

The present invention was achieved on the basis of these findings.

(First Embodiment)

With reference to FIGS. 5 and 6, a semiconductor device according to the first embodiment of the present invention is described. This semiconductor device is a semiconductor device that includes low dielectric constant films 105 a, 105 b and 105 c, of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings 123 which is a moisture blocking wall in closed loop form in a plan view, and where at least one of seal rings 123 includes a seal ring protrusion portion 10 in inward protruding form in the vicinity of a chip corner 4. Though seal ring protrusion portion 10 has effects to a certain degree only in the case where it is in inward protruding form in the vicinity of chip corner 4, here, it has a more preferable configuration, such that it has a seal ring diagonal side 9 which forms approximately equal angles with two chip end surfaces 5 and 6 that form chip corner 4, and which faces chip corner 4. Though seal ring protrusion portion 10 has effects to a certain degree only in the case where it has seal ring diagonal side 9, here, it has a more preferable configuration, where a first side 7 and a second side 8 which are parallel to two chip end surfaces 5 and 6, respectively, that form chip corner 4.

This semiconductor device is provided with a sacrifice pattern 124 which is a structure in wall form for preventing the progress of cracks outside of seal ring protrusion portion 10 from the center of the chip. FIG. 6 is a cross-sectional view along line VI-VI as viewed in the direction of the arrows. Sacrifice pattern 124 may have a configuration where the upper portion of seal ring 123 is omitted, that is to say, where a wall is constructed in the same manner as that of seal ring 123 only in the portion that corresponds to the layers of low dielectric constant films 105 a, 105 b and 105 c. Sacrifice pattern 124 that is to be a wall for preventing the progress of cracks has a structure where a number of wire layers are connected from the top and from the bottom through interlayer connection portions. The respective interlayer connection portions which are included in sacrifice pattern 124 are made of members in trench form instead of members in hole form.

Here, as shown in FIG. 7, sacrifice pattern 124 may have a structure where it reaches the same height as seal ring 123, that is to say, the layer of the aluminum wire. Alternatively, a configuration where sacrifice pattern 124 extends upward to the same height as wire 119 in the configuration of FIG. 6, that is to say, a configuration where the height of the sacrifice pattern is somewhere between that of FIG. 6 and FIG. 7, for example, may be provided.

Though one or more sacrifice patterns such as sacrifice pattern 124 can provide to a certain degree the effects of the present invention, it is preferable to provide a number of sacrifice patterns, and therefore, a sacrifice pattern group 3 is formed of a number of sacrifice patterns such as sacrifice pattern 124 in the example of FIG. 5. Sacrifice pattern group 3 includes a sacrifice pattern 13 in straight line form, in addition to a number of sacrifice patterns in bent line form, such as sacrifice pattern 124. Each of sacrifice pattern 124 in bent line form forms approximately the same angle with two chip end surfaces 5 and 6 that form chip corner 4, and has a sacrifice pattern diagonal side 11 that faces chip corner 4. The closer to the center of the chip the sacrifice pattern is, the longer sacrifice pattern diagonal side 11 is.

According to the present embodiment, at least one seal ring 123 has a form that includes a seal ring protrusion portion 10 in inward protruding form in the vicinity of a chip corner 4, and therefore, cracks that originate from chip corner 4 and progress hit the seal ring in a form that is close to the form that is drawn by the ends of actual cracks, and as a result, it becomes possible to prevent the progress of cracks efficiently. Furthermore, in the present embodiment, seal ring protruding portion 10 has seal ring diagonal side 9, and therefore, seal ring 123 stands parallel to the diagonal side portion in the center of the ends of progressing cracks. Accordingly, it becomes difficult for seal ring 123 to be destroyed by cracks. Furthermore, according to the present embodiment, seal ring protruding portion 10 has a first side 7 and a second side 8, and therefore, seal ring 123 has a number of portions which are arranged parallel to progressing cracks, such as bended lines 24 a and 24 b shown in FIG. 2, and thus, becomes strong against cracking.

According to the present embodiment, sacrifice pattern 124 is arranged so that cracks that progress so as to spread from chip corner 4 are prevented from progressing before they reach seal ring 123 when they reach sacrifice pattern 124. Sacrifice pattern 124 is, as a whole, a structure made of a metal in wall form using interlayer connection portions in trench form, and therefore, even in the case where cracks that have progressed along an interface on the lower side of one low dielectric constant film hit a wire layer of a certain height of sacrifice pattern 124 and avoid the wire layer so as to pass over the wire layer and progress through the low dielectric constant film above this low dielectric constant film, further progress can be prevented.

According to the present embodiment, as shown in FIG. 5, a number of sacrifice patterns 124 are provided, and this number of sacrifice patterns make the probability of stopping the progress of cracks before the cracks reach seal ring 123 high, even in the case where the cracks partially destroy sacrifice pattern 124 so as to further progress to the inside.

Furthermore, according to the present embodiment, each of sacrifice patterns 124 preferably has a sacrifice pattern diagonal side 11, and therefore, sacrifice pattern 124 stands parallel to a line drawn by the ends of cracking. Accordingly, sacrifice pattern 124 can effectively prevent the progress of cracks. Furthermore, the more cracks progress toward the center of the chip, the longer the diagonal side portion formed of the ends of cracks becomes, as shown in FIG. 2, and in the case where the semiconductor device is arranged in such a manner that the closer to the center of the chip, the longer sacrifice pattern diagonal side 11 becomes, as in the semiconductor device according to the present embodiment, sacrifice pattern diagonal side 11, which is longer than the previous one, is continuously hit by the diagonal side of the ends of cracks that becomes longer as cracks progress, and therefore, the progress of cracks can be effectively prevented.

In particular, in a preferable configuration, as shown in FIG. 5, a crack reaches seal ring 123 only in the case where all of sacrifice patterns 124 have been destroyed, and therefore, the function of sacrifice patterns 124, which are arranged in a limited area, can be most effectively utilized.

Here, though in the example shown in FIG. 5, sacrifice pattern group 3 includes a number of sacrifice patterns 13 in straight line form and a number of sacrifice patterns 24 in bent line form, as shown in FIG. 8, a sacrifice pattern group 14 where only a number of sacrifice patterns 13 in straight line form are arranged parallel to each other may be provided instead of sacrifice pattern group 3. Though in this case, lines drawn by the ends of progressing cracks and the forms of sacrifice patterns do not necessarily coincide completely, effects are gained where the progress can be prevented by the number of sacrifice patterns 13 which stand one after another against the progressing cracks, and in addition, the merit of simple design is gained. Sacrifice patterns 13 also have a sacrifice pattern diagonal side 11.

A configuration where only one sacrifice pattern 13 in straight line form is arranged, a configuration where only one sacrifice pattern 124 in bent line form and a configuration where only one sacrifice pattern 13 in straight line form and only one sacrifice pattern 124 in bent line form, that is to say, only two lines in total, are arranged within a region that is surrounded by seal ring protrusion portion 10 also fall within the scope intended by the technical idea of the present invention, although the effects of suppressing the progress of cracks are smaller, in comparison with the aforementioned examples.

Here, though it is preferable for the number of sacrifice patterns 124 that are included in sacrifice pattern group 3 to be arranged in such a manner that the sacrifice patterns 124 that are closer to the center the chip have a longer sacrifice pattern diagonal side 11, effects can be gained to a certain degree, even in the case where only some of the number of sacrifice patterns 124 that are included in sacrifice pattern group 3 are aligned in such an order, in addition to the case where all sacrifice patterns 124 that are included in sacrifice pattern group 3 are aligned in such an order. Accordingly, it can be said that it is preferable for at least some of the number of sacrifice patterns to be arranged in such a manner that the sacrifice patterns that are closer to the center of the chip have a longer sacrifice pattern diagonal side.

(Second Embodiment)

With reference to FIG. 9, a semiconductor device according to the second embodiment of the present invention is described. In this semiconductor device, a sacrifice pattern group 12 made of a number of sacrifice patterns is arranged within a region outside of a seal ring protrusion portion 10 from the center of the chip. Sacrifice pattern group 12 includes a sacrifice pattern in closed loop form. Preferably, as in the example shown in FIG. 9, sacrifice pattern group 12 includes a number of sacrifice patterns 23 in closed loop form, and the number of sacrifice patterns 23 in closed loop form are arranged in concentric form. The sacrifice patterns that are included in sacrifice pattern group 12 are parallel to seal ring 123 in the vicinity of seal ring 123. Some sacrifice patterns which are included in sacrifice pattern group 12 and in the vicinity of chip corner 4 are sacrifice patterns 13 in straight line form. The configuration of the other parts is the same as that described in the first embodiment.

According to the present embodiment, the group includes sacrifice patterns 23 in closed loop form, and therefore, moisture can be prevented from entering into the region surrounded by sacrifice patterns 23. Low dielectric constant films allow moisture to enter very easily, in comparison with silicon oxide films and the like. In the case where moisture enters into a low dielectric constant film, the physical strength further deteriorates, and moisture does not enter into the inside of sacrifice patterns 23 in closed loop form, as long as sacrifice patterns 23 are not destroyed, and therefore, deterioration in the physical strength of the low dielectric constant films can be prevented, and thus, the progress of cracks can be prevented. Particularly, in the case where a number of sacrifice patterns 23 in closed loop form are arranged in concentric form, the outermost sacrifice pattern 23 preferably provides broadly ranging collective regions into which no moisture enters. In the case where some sacrifice patterns in closed loop form on the outside are destroyed, some regions can be prevented from letting moisture in, if one or more sacrifice patterns in closed loop form remain on the inside.

Here, though the semiconductor device is provided with sacrifice pattern group 12 according to the present embodiment, an arrangement of only one sacrifice pattern in closed loop form, instead of sacrifice pattern group 12, has effects to a certain degree, even though the effects are inferior to the aforementioned example.

(Third Embodiment)

With reference to FIG. 10, a semiconductor device according to the third embodiment of the present invention is described. This semiconductor device corresponds to the example shown in FIG. 8 according to the first embodiment, where the seal ring is made double. That is to say, this semiconductor device is provided with a seal ring 123 a and a seal ring 123 b. A sacrifice pattern group 14 where a number of sacrifice patterns 13 in straight line form are provided is arranged outside of seal ring 123 a from the center of the chip. Respective sacrifice patterns 13 form approximately the same angle with two chip end surfaces 5 and 6 that form a chip corner 4, and are arranged so as to face chip corner 4.

According to the present embodiment, more than one seal ring is provided, so that the probability of destruction of the seal ring that is the closest to the center of the chip, and thus, hindering of the operation of the device can be made low when cracking progresses.

Though according to the present embodiment, the seal ring is double, it may be triple or more, instead of double. Here, it is necessary to note that the area that can be utilized inside of the seal rings decreases when the number of seal rings is increased. Though according to the present embodiment, a configuration where more than one seal ring is introduced into the example of FIG. 8, the same idea can be applied to other configurations. In the examples of FIGS. 5 and 9, for example, the seal ring may be made multiple. The seal ring may be made multiple also in the below described examples of FIGS. 11 to 13.

(Fourth Embodiment)

With reference to FIG. 11, a semiconductor device according to the fourth embodiment of the present invention is described. This semiconductor device is provided with a sacrifice pattern group 17 made of a number of sacrifice patterns. Sacrifice pattern group 17 includes an inner sacrifice pattern group 16 that is made of a number of sacrifice patterns 13 having sacrifice pattern diagonal sides 11 which form approximately the same angle with two chip end surfaces 5 and 6 that form a chip corner 4 and face chip corner 4, as well as a sacrifice pattern 15 in L shape which is arranged so as to surround inner sacrifice pattern group 16 from the outside and includes two sides which approximately form an L shape and are respectively parallel to two chip end surfaces 5 and 6 that form chip corner 4.

According to the present embodiment, sacrifice pattern 15 in L shape is provided, and therefore, initial cracks that have occurred, if any, from chip end surfaces 5 and 6 at the time of dicing of the wafer can be prevented from spreading to a certain degree, by sacrifice pattern 15 in L shape. In the case where cracks originating from these initial cracks progress toward the center of the chip during heat cycle testing, the number of sacrifice patterns 13 which are included inner sacrifice pattern group 16 prevent the progress of cracks. In this manner, the combination of sacrifice pattern 15 in L shape and inner sacrifice pattern group 16 makes prevention of the progress cracks effective. Here, though the example of FIG. 11 has one sacrifice pattern 15 in L shape, sacrifice pattern 15 in L shape may be double or more.

In addition, though the example of FIG. 11 has a configuration where sacrifice pattern 15 in L shape is combined with the example of FIG. 8, a sacrifice pattern in L shape may be combined to other embodiments.

(Fifth Embodiment)

With reference to FIG. 12, a semiconductor device according to the fifth embodiment of the present invention is described. This semiconductor device corresponds to a device that has a configuration where an outer seal ring 25 is added to the example shown in FIG. 8 according to the first embodiment. That is to say, this semiconductor device is provided with a sacrifice pattern group 14 made of a number of sacrifice patterns 13, and outer seal ring 25, which is a moisture blocking wall in closed loop form in a plan view, is provided so as to surround sacrifice pattern group 14 and seal ring 123 from the outside of this sacrifice pattern group 14. Though FIG. 12 shows only a portion of the semiconductor device, outer seal ring 25 is connected to a portion that is not shown and arranged in closed loop form along the outer line of the entirety of the semiconductor device. According to the present embodiment, outer seal ring 25 is provided, so that initial cracks that have occurred, if any, from chip end surfaces 5 and 6 at the time of dicing of the wafer can be prevented from spreading to a certain degree, by outer seal ring 25. Therefore, the same effects as those of the fourth embodiment can be gained. Furthermore, outer seal ring 25 has the function of preventing the inner region thereof from allowing moisture to enter, and therefore, the physical strength of the inner region of outer seal ring 25 can be prevented from deteriorating as a result of moisture that has entered.

Here, though outer seal ring 25 surrounds sacrifice pattern group 14 and seal ring 123 in the example of FIG. 12, an outer seal ring may be provided in the same manner, even in the case where there is only one sacrifice pattern instead of sacrifice pattern group 14.

Here, though one outer seal ring 25 is provided in the example of FIG. 12, outer seal rings 25 may be made double or more. In addition, though the example of FIG. 12 has a configuration where outer seal ring 25 is combined with the example of FIG. 8, an outer seal ring may be combined with other embodiments.

(Sixth Embodiment)

With reference to FIG. 13, a semiconductor device according to the sixth embodiment of the present invention is described. This semiconductor device is provided with a sacrifice pattern group 19. This semiconductor device corresponds to a device where sacrifice pattern group 14 is replaced with a sacrifice pattern group 19 in the example of FIG. 12. Though sacrifice pattern group 19 resembles sacrifice pattern group 14, it includes a linked layer 18 of which the portions are connected to each other. Sacrifice pattern group 19 is basically a collection of individual sacrifice patterns. In the example of FIG. 13, sacrifice pattern group 19 is a collection of a number of sacrifice patterns 26 in straight line form. Though sacrifice patterns 26 include a number of wire layers as viewed in the direction of the thickness, sacrifice patterns 26 are linked to each other in at least one layer from among the number of wire layers that exist in such a manner. The layer where sacrifice patterns are connected to each other in this manner is referred to as “linked layer” 18. It can be said that sacrifice pattern group 19 is a collection of the number of sacrifice patterns 26 in a state where they are linked to each other via linked layer 18.

According to the present embodiment, sacrifice patterns 26 are connected to each other by means of linked layer 18, and therefore, the strength of the entirety of sacrifice pattern group can be increased, and thus, the effect of opposing the progress of cracks can further be increased.

It is preferable for linked layer 18 to be in mesh form in a plan view, as in the example shown in FIG. 13. This is because such a structure can efficiently enhance the strength of the entirety. Here, the linked layer may be a single layer or made up of multiple layers.

Here, it is preferable for any of the aforementioned embodiments to have an arrangement where a sacrifice pattern blocks the lowest layer from among the low dielectric constant films. In the case where there is only one layer of a low dielectric constant film, “the lowest layer from among the low dielectric constant films” means this layer. Cracking easily occurs in the lowest layer from among the low dielectric constant films, and therefore, in the case where a sacrifice pattern is arranged so as to block the lowest layer from among the low dielectric constant films, the same phenomenon as that where cracks reach seal ring 123 after they have progressed along the interface on the lower side of a low dielectric constant film in FIG. 3 occurs for cracks and the sacrifice pattern in this case. That is to say, the effects become significant, particularly in terms of preventing the progress of cracks. It is preferable for a sacrifice pattern to be arranged so as to block the interface on the lower side of the lowest layer from among the low dielectric constant films.

Significant effects can be gained also in a semiconductor device that includes a number of low dielectric constant films according to the present invention. It is preferable for sacrifice patterns to be arranged so as to block all of the number of low dielectric constant films in the semiconductor device that includes the number of low dielectric constant films. As described with reference to FIG. 4, cracks tend to continuously progress by avoiding wire layers by passing over the wire layers and progressing through the layers above the wire layers when they reach the wire layers while progressing. In the case where sacrifice patterns are arranged so as to block all of the number of low dielectric constant films, however, cracking can be effectively prevented, even when cracks pass over the wire layers and into the layers above the wire layers, and thus, this is preferable.

Furthermore, it is preferable for all of the aforementioned embodiments to have an arrangement where a sacrifice pattern is separated from a seal ring in a plan view. In all of the aforementioned illustrations, the sacrifice patterns are arranged so as to be separated from the seal rings in a plan view, and this can lower the probability of a state occurring where the seal rings are peeled by being pulled by the displacement of a peeling portion, in the case where a sacrifice pattern is destroyed and peels.

Here, where, in each of the aforementioned embodiments, the expression “forms approximately the same angle with two chip end surfaces 5 and 6 that form a chip corner 4” is used when referring to the state of sealing diagonal side 9, sacrifice pattern diagonal side 11 and the like, this means a case where angles of 40° to 50° are formed for chip corner 4 that forms, for example, a right angle, in addition to a case where an angle of 45° is formed with the two respective chip end surfaces 5 and 6. That is to say, a state where a diagonal side is inclined at 40° relative to chip end surface 5 and inclined at 50° relative to chip end surface 6, for example, is also included in the expression. Here, a case where an angle of approximately 45° is formed for both of chip end surfaces 5 and 6 is most preferable. This is because such an arrangement can make the diagonal side oppose progressing cracks precisely head-on.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims. 

1. A semiconductor device, comprising a low dielectric constant film having a relative dielectric constant less than 3.5, and a seal ring which is a moisture blocking wall forming a closed loop in a plan view, wherein said seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of a chip, wherein a passivation film covers said low dielectric constant film and the seal ring, and has a opening penetrating the passivation film, the opening formed in a vicinity of two chip end surfaces in a plan view, said two chip end surfaces forming the corner of the chip.
 2. The semiconductor device according to claim 1, wherein a sacrifice pattern is provided outside of said sealing protrusion portion of the seal ring from a center of a chip, wherein the sacrifice pattern is a structure in wall-form for preventing progress of a crack.
 3. The semiconductor device according to claim 2, wherein said seal rings includes a Cu seal ring and A1 seal ring formed above said Cu seal ring, and wherein said sacrifice pattern includes a Cu sacrifice pattern.
 4. The semiconductor device according to claim 2, wherein said passivation film is made of a SiN, wherein said seal rings includes a Cu seal ring and A1 seal ring formed above said Cu seal ring and said sacrifice pattern includes a Cu sacrifice pattern, and wherein an A1 sacrifice pattern is not formed above said sacrifice pattern.
 5. The semiconductor device according to claim 4, wherein said sacrifice pattern has a sacrifice pattern diagonal side which forms approximately a same angle with the two chip end surfaces that form said corner, and has a sacrifice pattern diagonal side that faces said corner.
 6. The semiconductor device according to claim 4, wherein said sacrifice pattern is a sacrifice pattern forming a closed loop.
 7. The semiconductor device according to claim 4, comprising: a sacrifice pattern group that includes a plurality of the sacrifice patterns.
 8. The semiconductor device according to claim 7, wherein the plurality of the sacrifice patterns included in said sacrifice pattern group respectively have a sacrifice pattern diagonal side which forms approximately a same angle with the two chip end surfaces that form said corner and faces said corner.
 9. The semiconductor device according to claim 8, wherein at least some of said plurality of the sacrifice patterns are arranged so that sacrifice patterns that are closer to the center of the chip have a longer sacrifice pattern diagonal side.
 10. The semiconductor device according to claim 1, wherein said seal ring protrusion portion protrudes toward a center of said chip, and said seal ring protrusion portion forms approximately a same angle with the two chip end surfaces that form said corner of the chip, and has a sealing diagonal side that faces said corner of the chip.
 11. The semiconductor device according to claim 7, wherein said sacrifice pattern group includes a number of sacrifice patterns forming a closed loop, and said number of sacrifice patterns forming a closed loop are arranged in concentric form.
 12. The semiconductor device according to claim 7, wherein said sacrifice pattern group includes an inner sacrifice pattern group having a sacrifice pattern diagonal side which forms approximately a same angle with the two chip end surfaces that form said corner and faces said corner, and a sacrifice pattern in L shape which is configured to surround said inner sacrifice pattern group from outside and includes two sides which approximately form an L shape and are respectively parallel to the two chip end surfaces that form said corner.
 13. The semiconductor device according to claim 7, wherein said plurality of the sacrifice patterns has a linked layer of which the portions are connected to each other.
 14. The semiconductor device according to claim 13, wherein said linked layer is in mesh form in a plan view.
 15. The semiconductor device according to claim 4, further comprising: a number of low dielectric constant films that include said low dielectric constant film, wherein said sacrifice pattern is configured to block the lowest layer from among said low dielectric constant films.
 16. The semiconductor device according to claim 4, further comprising: a number of low dielectric constant films that include said low dielectric constant film, wherein said sacrifice pattern are configured to block all of said number of low dielectric constant films.
 17. The semiconductor device according to claim 1, wherein the opening is arranged outside of a region surrounded by the seal ring in a plan view.
 18. The semiconductor device according to claim 4, wherein said sacrifice pattern is configured to be separated from said seal ring in a plan view.
 19. A semiconductor device, comprising: a first insulating layer; a second insulating layer including a low dielectric constant film of which a relative dielectric constant is less than 3.5; a third insulating layer; a semiconductor substrate; a seal ring forming a closed loop in a plan view; and a fourth insulating layer which is made of SiN having an opening penetrating the fourth insulating film and covering said third insulating layer and the seal ring, the opening formed in a vicinity of two chip end surfaces in a plan view, said two chip end surfaces forming a corner of a chip, wherein said semiconductor substrate, said first insulating layer, said second insulating layer and said third insulating layer are layered in order of said semiconductor substrate, said first insulating layer, said second insulating layer, said third insulating layer, respectively, the seal ring is formed in said first insulating layer, said second insulating layer and said third insulating layer on said semiconductor substrate, said seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of the corner of the chip, said seal ring protrusion portion protrudes toward a center of said chip between said first insulating layer and said low dielectric constant film, and said relative dielectric constant of said low dielectric constant film is less than a relative dielectric constant of said first insulating layer.
 20. The semiconductor device according to claim 19, wherein said seal ring protrusion portion has a first side and a second side which are respectively parallel to the two chip end surfaces that form said corner, and wherein said seal ring is polygonal shape along an outer periphery of the chip in the plan view.
 21. The semiconductor device according to claim 19, further comprising: a sacrifice pattern provided outside of said seal ring protrusion portion from said center of the chip, and wherein the sacrifice pattern is separated from said seal ring.
 22. The semiconductor device according to claim 21, wherein said seal ring is formed on said third insulating layer and said sacrifice pattern is not formed on said third insulating laver.
 23. The semiconductor device according to claim 19, wherein said seal ring is a moisture blocking wall, and wherein said seal ring protrusion portion forms approximately a same angle with the two chip end surfaces that form said corner of the chip, and has a sealing diagonal side that faces said corner of the chip.
 24. The semiconductor device according to claim 21, further comprising: a resin covering the semiconductor device, wherein said seal ring includes a Cu seal ring and A1 seal ring formed above said Cu seal ring and said sacrifice pattern includes a Cu sacrifice pattern, wherein an A1 sacrifice pattern is not formed above said sacrifice pattern, and wherein the sacrifice pattern is a structure in wall-form for preventing progress of a crack.
 25. A semiconductor device, comprising: a semiconductor substrate; a first insulating layer formed over said semiconductor substrate; a second insulating layer including a low dielectric constant film having a relative dielectric constant less than 3.5, said second insulating layer formed over said first insulating layer; a third insulating layer formed over said second insulating layer; a seal ring forming a closed loop in a plan view; and a fourth insulating layer which is made of a SiN having an opening penetrating the fourth insulating film, and covering said third insulating layer and said seal ring, the opening formed in a vicinity of first and second chip end surfaces in a plan view, wherein said seal ring is formed in said first insulating layer, said second insulating layer and said third insulating layer on said semiconductor substrate, said seal ring includes a first side formed along the first chip end surface, a second side formed approximately in parallel to the second chip end surface, a third side formed approximately in parallel to said first chip end surface, and a fourth side formed along the second chip end surface in a vicinity of a chip corner, said first chip end surface and said second chip end surface forming said chip corner, said second side formed between said first side and said third side, and said third side formed between said second side and said fourth side, one end of said first side is electrically coupled to one end of said second side, another end of said second side is electrically coupled to one end of said third side, and another end of said third side is electrically coupled to one end of said fourth side, and said first side, said second side, said third side, and said fourth side are formed between said first insulating layer and said low dielectric constant film, and wherein said relative dielectric constant of said low dielectric constant film is less than a relative dielectric constant of said first insulating layer.
 26. The semiconductor device according to claim 25, further comprising: a sacrifice pattern, wherein said sacrifice pattern is provided outside of said second side of the seal ring and said third side of the seal ring from center of a semiconductor chip, and wherein the sacrifice pattern is separated from said seal ring.
 27. The semiconductor device according to claim 25, wherein said second side and said third side are configured to prevent progress of a crack occurring between said first insulating layer and said low dielectric constant film, and wherein said sacrifice pattern is configured to prevent progress of the crack.
 28. The semiconductor device according to claim 26, wherein said seal ring is formed on said third insulating layer and said sacrifice pattern is not formed on said third insulating laver.
 29. The semiconductor device according to claim 26, wherein said seal ring is a moisture blocking wall, and wherein said sacrifice pattern has a structure in a wall form that is configured to prevent progress of the crack.
 30. The semiconductor device according to claim 25, wherein the opening is arranged outside of a region surrounded by the seal ring in a plan view.
 31. The semiconductor device according to claim 25, further comprising: a resin covering the semiconductor device.
 32. The semiconductor device according to claim 25, wherein said seal ring has a polygonal shape along outer periphery of a semiconductor chip in a plan view.
 33. The semiconductor device according to claim 26, wherein said seal ring includes a Cu seal ring and A1 seal ring formed above said Cu seal ring, and said sacrifice pattern includes a Cu sacrifice pattern, wherein an A1 sacrifice pattern is not formed above said sacrifice pattern.
 34. The semiconductor device according to claim 25, wherein said seal ring includes a fifth side facing said chip corner, said fifth side forming approximately a same angle with said first chip end surface and said second chip end surface, said fifth side formed between said second side and said third side.
 35. The semiconductor device according to claim 26, wherein said sacrifice pattern is a sacrifice pattern forming a closed loop.
 36. The semiconductor device according to claim 25, wherein said seal ring includes a fifth side, the another end of said second side is electrically coupled to one end of said third side via said fifth side, said fifth side facing said chip corner, one end of said fifth side electrically coupled to another end of said second side, and another end of said fifth side electrically coupled to one end of said third side.
 37. The semiconductor device according to claim 36, wherein said fifth side forms approximately a same angle with said first chip end surface and said second chip end surface.
 38. A semiconductor device, comprising: a chip; and a low dielectric constant film having a relative dielectric constant less than 3.5; and a seal ring which is a moisture blocking wall in closed loop form in a plan view, wherein the seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of the chip, the seal ring comprising 16 lengths arranged to circumscribe a center point of a surface of said chip, with length 1 connected to length 2, length 2 connected to length 3, length 3 connected to length 4, length 4 connected to length 5, length 5 connected to length 6, length 6 connected to length 7, length 7 connected to length 8, length 8 connected to length 9, length 9 connected to length 10, length 10 connected to length 11, length 11 connected to length 12, length 12 connected to length 13, length 13 connected to length 14, length 14 connected to length 15, length 15 connected to length 16, and length 16 connected to length 1, and length 1 is parallel to length 9, length 5 is parallel to length 13, length 3 is parallel to length 11, length 7 is parallel to length 15, length 2 is parallel to length 16, length 4 is parallel to length 6, length 8 is parallel to length 10, and length 12 is parallel to length 14, wherein a passivation film covers said low dielectric constant film and said seal ring and has a opening penetrating the passivation film, the opening formed in a vicinity of first and second chip end surfaces in a plan view, said first and said second chip end surfaces forming the corner of the chip.
 39. The semiconductor device according to claim 38, wherein a sacrifice pattern is provided outside of said sealing protrusion portion of the seal ring from the center of the chip.
 40. The semiconductor device according to claim 39, wherein said sacrifice pattern has a structure in a wall form that is configured to prevent progress of the crack, and wherein the sacrifice pattern is separated from said seal ring.
 41. A semiconductor device, comprising: a low dielectric constant film having a relative dielectric constant less than 3.5; a seal ring which forming a moisture blocking wall having a closed loop in a plan view; and an outer seal ring surrounding the seal ring, wherein said seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of a chip, wherein a passivation film covers said low dielectric constant film and the seal ring, and has an opening penetrating the passivation film, the opening arranged outside of a region surrounded by the seal ring in a plan view.
 42. The semiconductor device according to claim 41, wherein a sacrifice pattern is provided outside of said sealing protrusion portion of the seal ring from a center of a chip, wherein the sacrifice pattern is a structure in wall-form for preventing progress of a crack.
 43. The semiconductor device according to claim 42, wherein said seal rings includes a Cu seal ring and A1 seal ring formed above said Cu seal ring, and wherein said sacrifice pattern includes a Cu sacrifice pattern.
 44. The semiconductor device according to claim 42, wherein said passivation film is made of a SiN, wherein said seal rings includes a Cu seal ring and A1 seal ring formed above said Cu seal ring and said sacrifice pattern includes a Cu sacrifice pattern, and wherein an A1 sacrifice pattern is not formed above said sacrifice pattern.
 45. The semiconductor device according to claim 44, wherein said sacrifice pattern has a sacrifice pattern diagonal side which forms approximately a same angle with two chip end surfaces that form said corner, and has a sacrifice pattern diagonal side that faces said corner.
 46. The semiconductor device according to claim 44, wherein said sacrifice pattern is a sacrifice pattern in closed loop form.
 47. The semiconductor device according to claim 44, comprising: a sacrifice pattern group that includes a plurality of the sacrifice patterns.
 48. The semiconductor device according to claim 47, wherein the plurality of the sacrifice patterns included in said sacrifice pattern group respectively have a sacrifice pattern diagonal side which forms approximately a same angle with two chip end surfaces that form said corner and faces said corner.
 49. The semiconductor device according to claim 48, wherein at least some of said plurality of the sacrifice patterns are arranged so that sacrifice patterns that are closer to the center of the chip have a longer sacrifice pattern diagonal side.
 50. The semiconductor device according to claim 41, wherein said seal ring protrusion portion protrudes toward a center of said chip, and said seal ring protrusion portion forms approximately a same angle with two chip end surfaces that form said corner of the chip, and has a sealing diagonal side that faces said corner of the chip.
 51. The semiconductor device according to claim 47, wherein said sacrifice pattern group includes a number of sacrifice patterns forming closed loops, and said number of sacrifice patterns in closed loops are arranged in concentrically.
 52. The semiconductor device according to claim 47, wherein said sacrifice pattern group includes an inner sacrifice pattern group having a sacrifice pattern diagonal side which forms approximately a same angle with two chip end surfaces that form said corner and faces said corner, and a sacrifice pattern in L shape which is configured to surround said inner sacrifice pattern group from outside and includes two sides which approximately form an L shape and are respectively parallel to the two chip end surfaces that form said corner.
 53. The semiconductor device according to claim 47, wherein said plurality of the sacrifice patterns has a linked layer of which the portions are connected to each other.
 54. The semiconductor device according to claim 53, wherein said linked layer is in mesh form in a plan view.
 55. The semiconductor device according to claim 44, further comprising: a number of low dielectric constant films that include said low dielectric constant film, wherein said sacrifice pattern is configured to block the lowest layer from among said low dielectric constant films.
 56. The semiconductor device according to claim 44, further comprising: a number of low dielectric constant films that include said low dielectric constant film, wherein said sacrifice pattern is configured to block all of said number of low dielectric constant films.
 57. The semiconductor device according to claim 41, wherein the opening is formed in the vicinity of the corner of the chip in a plan view.
 58. The semiconductor device according to claim 44, wherein said sacrifice pattern is configured to be separated from said seal ring in a plan view.
 59. A semiconductor device, comprising: a first insulating layer; a second insulating layer including a low dielectric constant film of which a relative dielectric constant is less than 3.5; a third insulating layer; a semiconductor substrate; a seal ring forming a closed loop in a plan view; an outer seal ring surrounding the seal ring; and a fourth insulating layer which is made of SiN having an opening penetrating the fourth insulating film and covering said third insulating layer, the seal ring, and the outer seal ring, the opening arranged outside of a region surrounded by the seal ring in a plan view, wherein said semiconductor substrate, said first insulating layer, said second insulating layer and said third insulating layer are layered in order of said semiconductor substrate, said first insulating layer, said second insulating layer, said third insulating layer, respectively, each of the seal ring and the outer seal ring is formed in said first insulating layer, said second insulating layer and said third insulating layer on said semiconductor substrate, said seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of a chip, said seal ring protrusion portion protrudes toward a center of said chip between said first insulating layer and said low dielectric constant film, and said relative dielectric constant of said low dielectric constant film is less than a relative dielectric constant of said first insulating layer.
 60. The semiconductor device according to claim 59, wherein said seal ring protrusion portion has a first side and a second side which are respectively parallel to the two chip end surfaces that form said corner, and wherein said seal ring has a polygonal shape along an outer periphery of the chip in the plan view.
 61. The semiconductor device according to claim 59, further comprising: a sacrifice pattern is provided outside of said seal ring protrusion portion from said center of the chip, and wherein the sacrifice pattern is separated from said seal ring.
 62. The semiconductor device according to claim 61, wherein said seal ring is formed on said third insulating layer and said sacrifice pattern is not formed on said third insulating laver.
 63. The semiconductor device according to claim 59, wherein said seal ring is a moisture blocking wall, and wherein said seal ring protrusion portion forms approximately a same angle with two chip end surfaces that form said corner of the chip, and has a sealing diagonal side that faces said corner of the chip.
 64. The semiconductor device according to claim 61, further comprising: a resin covering the semiconductor device, wherein said seal ring includes a Cu seal ring and A1 seal ring formed above said Cu seal ring and said sacrifice pattern includes a Cu sacrifice pattern, wherein an A1 sacrifice pattern is not formed above said sacrifice pattern, and wherein the sacrifice pattern has a wall-form for preventing progress of a crack.
 65. A semiconductor device, comprising: a semiconductor substrate; a first insulating layer formed over said semiconductor substrate; a second insulating layer including a low dielectric constant film having a relative dielectric constant less than 3.5, said second insulating layer formed over said first insulating layer; a third insulating layer formed over said second insulating layer; a seal ring forming a closed loop in a plan view; an outer seal ring surrounding the seal ring; and a fourth insulating layer which is made of a SiN, has a opening penetrating the fourth insulating film, and covers said third insulating laver, said seal ring, and the outer seal ring, the opening arranged outside of a region surrounded by the seal ring in a plan view, wherein said seal ring is formed in said first insulating layer, said second insulating layer and said third insulating layer on said semiconductor substrate, said seal ring includes a first side formed along a first chip end surface, a second side formed approximately in parallel to a second chip end surface, a third side formed approximately in parallel to said first chip end surface, and a fourth side formed along the second chip end surface in a vicinity of a chip corner, said first chip end surface and said second chip end surface forming said chip corner, said second side formed between said first side and said third side, and said third side formed between said second side and said fourth side, one end of said first side is electrically coupled to one end of said second side, another end of said second side is electrically coupled to one end of said third side, and another end of said third side is electrically coupled to one end of said fourth side, and said first side, said second side, said third side, and said fourth side are formed between said first insulating layer and said low dielectric constant film, and said relative dielectric constant of said low dielectric constant film is less than a relative dielectric constant of said first insulating layer.
 66. The semiconductor device according to claim 65, further comprising: a sacrifice pattern, and wherein said sacrifice pattern is provided outside of said second side of the seal ring and said third side of the seal ring from center of a semiconductor chip, wherein the sacrifice pattern is separated from said seal ring.
 67. The semiconductor device according to claim 65, wherein said second side and said third side are configured to prevent progress of a crack occurring between said first insulating layer and said low dielectric constant film, and wherein said sacrifice pattern is configured to prevent progress of the crack.
 68. The semiconductor device according to claim 66, wherein said seal ring is formed on said third insulating layer and said sacrifice pattern is not formed on said third insulating laver.
 69. The semiconductor device according to claim 66, wherein said seal ring is a moisture blocking wall, and wherein said sacrifice pattern has a wall form structure that is configured to prevent progress of the crack.
 70. The semiconductor device according to claim 65, wherein the opening is formed in a vicinity of the first and second chip end surfaces in a plan view.
 71. The semiconductor device according to claim 65, further comprising: a resin covering the semiconductor device.
 72. The semiconductor device according to claim 65, wherein said seal ring is polygonal shape along outer periphery of a semiconductor chip in a plan view.
 73. The semiconductor device according to claim 66, wherein said seal ring includes a Cu seal ring and A1 seal ring formed above said Cu seal ring, and said sacrifice pattern includes a Cu sacrifice pattern, wherein an A1 sacrifice pattern is not formed above said sacrifice pattern.
 74. The semiconductor device according to claim 65, wherein said seal ring includes a fifth side facing said chip corner, said fifth side forming approximately a same angle with said first chip end surface and said second chip end surface, said fifth side formed between said second side and said third side.
 75. The semiconductor device according to claim 66, wherein said sacrifice pattern has a closed loop form.
 76. The semiconductor device according to claim 65, wherein said seal ring includes a fifth side, the another end of said second side is electrically coupled to one end of said third side via said fifth side, said fifth side facing said chip corner, one end of said fifth side electrically coupled to another end of said second side, and another end of said fifth side electrically coupled to one end of said third side.
 77. The semiconductor device according to claim 76, wherein said fifth side forms approximately a same angle with said first chip end surface and said second chip end surface.
 78. A semiconductor device, comprising: a chip; and a low dielectric constant film having a relative dielectric constant less than 3.5; a seal ring which is a moisture blocking wall forming a closed loop in a plan view; and an outer seal ring surrounding the seal ring, wherein the seal ring includes a seal ring protrusion portion in inward protruding form in a vicinity of a corner of the chip, the seal ring comprising 16 lengths arranged to circumscribe a center point of a surface of said chip, with length 1 connected to length 2, length 2 connected to length 3, length 3 connected to length 4, length 4 connected to length 5, length 5 connected to length 6, length 6 connected to length 7, length 7 connected to length 8, length 8 connected to length 9, length 9 connected to length 10, length 10 connected to length 11, length 11 connected to length 12, length 12 connected to length 13, length 13 connected to length 14, length 14 connected to length 15, length 15 connected to length 16, and length 16 connected to length 1, and length 1 is parallel to length 9, length 5 is parallel to length 13, length 3 is parallel to length 11, length 7 is parallel to length 15, length 2 is parallel to length 16, length 4 is parallel to length 6, length 8 is parallel to length 10, and length 12 is parallel to length 14, wherein a passivation film covers said low dielectric constant film and said seal ring and has a opening penetrating the passivation film, the opening arranged outside of a region surrounded by the seal ring in a plan view.
 79. The semiconductor device according to claim 78, wherein a sacrifice pattern is provided outside of said sealing protrusion portion of the seal ring from the center of the chip.
 80. The semiconductor device according to claim 79, wherein said sacrifice pattern has a wall form structure that is configured to prevent progress of the crack, and wherein the sacrifice pattern is separated from said seal ring. 